View RFD16N03L_148312.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

SEMICONDUCTOR
RFD16N03L, RFD16N03LSM
16A, 30V, Avalanche Rated N-Channel Logic Level Enhancement-Mode Power MOSFETs
Packaging
JEDEC TO-251AA
SOURCE DRAIN GATE DRAIN (FLANGE)
December 1995
Features
* 16A, 30V * rDS(ON) = 0.022 * Temperature Compensating PSPICE Model * Can be Driven Directly from CMOS, NMOS, and TTL Circuits * Peak Current vs Pulse Width Curve * UIS Rating Curve * +175
oC
JEDEC TO-252AA
DRAIN (FLANGE)
Operating Temperature
Description
The RFD16N03L and RFD16N03LSM are N-channel power MOSFETs manufactured using the MegaFET process. This process, which uses feature sizes approaching those of LSI circuits, gives optimum utilization of silicon, resulting in outstanding performance. They were designed for use in applications such as switching regulators, switching converters, motor drivers and relay drivers. This performance is accomplished through a special gate oxide design which provides full rated conductance at gate bias in the 3V - 5V range, thereby facilitating true on-off power control directly from logic level (5V) integrated circuits.
PACKAGE AVAILABILITY PART NUMBER RFD16N03L RFD16N03LSM PACKAGE TO-251AA TO-252AA BRAND 16N03L 16N03L
GATE SOURCE
Symbol
DRAIN
GATE
SOURCE
NOTE: When ordering, use the entire part number. Add the suffix 9A, to obtain the TO-252AA variant in tape and reel, e.g. RFD16N03LSM9A.
Formerly developmental type TA49030.
Absolute Maximum Ratings
TC = +25oC RFD16N03L, RFD16N03LSM 30 30 10 16 Refer to Peak Current Curve Refer to UIS Curve 90 0.606 -55 to +175 260 UNITS V V V A
Drain-Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain-Gate Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate-Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Drain Current RMS Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EAS Power Dissipation TC = +25o C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate above +25o C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TSTG, TJ Soldering Temperature of Leads for 10s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
W W/oC oC oC
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper ESD Handling Procedures. Copyright
(c) Harris Corporation 1995
File Number
4013.1
5-31
Specifications RFD16N03L, RFD16N03LSM
Electrical Specifications
PARAMETERS Drain-Source Breakdown Voltage Gate Threshold Voltage Zero Gate Voltage Drain Current TC = +25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS TEST CONDITIONS ID = 250A, VGS = 0V VGS = VDS, ID = 250A VDS = 30V, VGS = 0V VGS = 10V ID = 16A, VGS = 5V VDD = 15V, ID = 16A, RL = 0.93, VGS = 5V, RGS = 5 TC = +25oC TC = +150oC MIN 30 1 VGS = 0V to 10V VGS = 0V to 5V VGS = 0V to 1V VDS = 25V, VGS = 0V, f = 1MHz VDD = 24V, ID = 16A, RL = 1.5 TO-251 and TO-252 TYP 15 95 25 27 50 30 1.5 1650 575 200 MAX 2 1 50 100 0.022 120 80 60 36 1.8 1.65 100 UNITS V V A A nA ns ns ns ns ns ns nC nC nC pF pF pF
oC/W oC/W
Gate-Source Leakage Current On Resistance Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Total Gate Charge Gate Charge at 5V Threshold Gate Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Thermal Resistance Junction-to-Case Thermal Resistance Junction-to-Ambient
IGSS rDS(ON) tON tD(ON) tR tD(OFF) tF tOFF QG(TOT) QG(5) QG(TH) CISS COSS CRSS RJC RJA
Source-Drain Diode Specifications
PARAMETERS Forward Voltage Reverse Recovery Time SYMBOL VSD tRR TEST CONDITIONS ISD = 16A ISD = 16A, dISD/dt = 100A/s MIN TYP MAX 1.5 75 UNITS V ns
5-32
RFD16N03L, RFD16N03LSM Typical Performance Curves
TC = +25oC 500 2 1 ID, DRAIN CURRENT (A) ZJC, NORMALIZED THERMAL RESPONSE 100 100s 1ms 10 10ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 1 1 10 VDS, DRAIN-TO-SOURCE VOLTAGE (V) 50 100ms DC 0.5 0.2 PDM 0.1 0.1 .05 .02 .01 SINGLE PULSE 0.01 10-5 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC + TC 101
VDSS MAX = 30V
10-4 10-3 10-2 10-1 100 t, RECTANGULAR PULSE DURATION (s)
FIGURE 1. SAFE OPERATING AREA CURVE
FIGURE 2. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
20 500 IDM, PEAK CURRENT CAPABILITY (A) VGS = 10V VGS = 5V ID, DRAIN CURRENT (A)
TC = +25oC FOR TEMPERATURES ABOVE +25oC DERATE PEAK CURRENT AS FOLLOWS: I
15
= I25
100
175 - TC 150
10
5
TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION
0 25 50 75 100 125 TC, CASE TEMPERATURE (oC) 150 175
10 10-5
10-4
10-3 10-2 10-1 t, PULSE WIDTH (s)
100
101
FIGURE 3. MAXIMUM CONTINUOUS DRAIN CURRENT vs TEMPERATURE
FIGURE 4. PEAK CURRENT CAPABILITY
PULSE DURATION = 250s, TC = +25oC ID(ON), ON-STATE DRAIN CURRENT (A) 100 VGS = 10V ID, DRAIN CURRENT (A) 75 VGS = 4.5V VGS = 4V VGS = 5V
VDD = 15V 100 -55oC +175oC
75 +25oC 50
50
25
VGS = 3.5V VGS = 3V
25 PULSE TEST PULSE DURATION = 250s DUTY CYCLE = 0.5% MAX 0 0 1.5 3.0 4.5 6.0 VGS, GATE-TO-SOURCE VOLTAGE (V) 7.5
0 0 1.0 2.0 3.0 4.0 5.0 VDS, DRAIN-TO-SOURCE VOLTAGE (V)
FIGURE 5. TYPICAL SATURATION CHARACTERISTICS
FIGURE 6. TYPICAL TRANSFER CHARACTERISTICS
5-33
RFD16N03L, RFD16N03LSM Typical Performance Curves (Continued)
BVDSS, NORMALIZED DRAIN-TO-SOURCE BREAKDOWN VOLTAGE ID = 250A 2.0 VGS(TH), NORMALIZED GATE THRESHOLD VOLTAGE 2.0 VGS = VDS, ID = 250A
1.5
1.5
1.0
1.0
0.5
0.5
0.0 -80
-40
0
40
80
120
160
200
0.0 -80
-40
TJ , JUNCTION TEMPERATURE (oC)
0 40 80 120 TJ, JUNCTION TEMPERATURE (oC)
160
200
FIGURE 7. NORMALIZED DRAIN-SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 8. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE
PULSE DURATION = 250s, VGS = 5V, ID = 16A rDS(ON), NORMALIZED ON RESISTANCE rDS(ON), ON-STATE RESISTANCE (m) 2.0 100
TJ = 25oC, PULSE DURATION = 250s
ID = 32A 75 ID = 16A ID = 8A 50 ID = 2A
1.5
1.0
0.5
25
0.0 -80 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC)
0 2.5
3.0
3.5
4.0
4.5
5.0
VGS, GATE-TO-SOURCE VOLTAGE (V)
FIGURE 9. NORMALIZED rDS(ON) vs JUNCTION TEMPERATURE
FIGURE 10. TYPICAL rDS(ON) FOR VARYING CONDITIONS OF GATE VOLTAGE AND DRAIN CURRENT
VDD = 15V, IDD = 16A, RL = 0.93 VDS , DRAIN-SOURCE VOLTAGE (V) 250 tR
30 VDD = BVDSS 24 VDD = BVDSS
5 VGS , GATE-SOURCE VOLTAGE (V)
200 SWITCHING TIME (ns) tF 150 tD(ON) 100 tD(OFF) 50
4
18
3
12
0.75 BVDSS 0.50 BVDSS 0.25 BVDSS RL = 1.875 IG(REF) = 0.6mA VGS = 5V IG(REF) IG(ACT) IG(REF) IG(ACT)
2
6
1
0 0 10 20 30 40 RGS, GATE-TO-SOURCE RESISTANCE () 50
0 20
0
t, TIME (s)
80
FIGURE 11. TYPICAL SWITCHING TIME AS A FUNCTION OF GATE RESISTANCE
FIGURE 12. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT. REFER TO HARRIS APPLICATION NOTES AN7254 AND AN7260
5-34
RFD16N03L, RFD16N03LSM Typical Performance Curves (Continued)
200 VGS = 0V, f = 1MHz IAS, AVALANCHE CURRENT (A) 2500 100 STARTING TJ = +25oC
C, CAPACITANCE (pF)
2000
CISS
1500
10
STARTING TJ = +150oC
1000 COSS 500 CRSS
If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV=(L/R)ln[(IAS*R)/(1.3*RATED BVDSS-VDD) +1] 1 0.001 0.01 0.1 1 10 tAV, TIME IN AVALANCHE (ms) 100
0
0
5 10 15 20 VDS, DRAIN-TO-SOURCE VOLTAGE (V)
25
FIGURE 13. TYPICAL CAPACITANCE vs VOLTAGE
FIGURE 14. UNCLAMPED INDUCTIVE SWITCHING. REFER TO HARRIS APPLICATION NOTES AN9321 AND AN9322
1.2 POWER DISSIPATION MULTIPLIER 1.0 0.8 0.6 0.4 0.2 0.0
0
25
50 75 100 125 TC , CASE TEMPERATURE (oC)
150
175
FIGURE 15. NORMALIZED POWER DISSIPATION vs TEMPERATURE DERATING CURVE
5-35
RFD16N03L, RFD16N03LSM Test Circuits and Waveforms
VDS tP L IAS VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG +
BVDSS VDS VDD
VDD
0V
IL 0.01 tAV
FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 17. UNCLAMPED ENERGY WAVEFORMS
VDD RL VDS VDS VGS
tON tD(ON) tR 90%
tOFF tD(OFF) tF 90%
10%
10% 90%
0V
RGS
DUT
VGS 10% 50% PULSE WIDTH
50%
FIGURE 18. RESISTIVE SWITCHING TEST CIRCUIT
FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
5-36
RFD16N03L, RFD16N03LSM Temperature Compensated PSPICE Model for the RFD16N03L, RFD16N03LSM
.SUBCKT RFD16N03L 2 1 3; CA 12 8 2.55e-9 CB 15 14 2.64e-9 CIN 6 8 1.45e-9 DBODY 7 5 DBDMOD DBREAK 5 11 DBKMOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 7 17 18 33.3 EDS 14 8 5 8 EGS 13 8 6 8 ESG 6 10 6 8 EVTO 20 6 18 IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 3.4e-9 LSOURCE 3 7 3.4e-9 MOS1 16 6 8 8 MOSMOD M = 0.99 MOS2 16 21 8 8 MOSMOD M = 0.01 RBREAK 17 18 RBKMOD 1 RDRAIN 50 16 RDSMOD 0.14e-3 RGATE 9 20 0.89 RIN 6 8 1e9 RSCL1 5 51 RSCLMOD 1e-6 RSCL2 5 50 1e3 RSOURCE 8 7 RDSMOD 10.31e-3 RVTO 18 19 RVTOMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD
S1A 12 S1B CA + EGS 6 8 EDS 13 8 14 13 13 S2A 15 S2B CB + 5 8 14 IT RBREAK 17 18 RVTO 19 VBAT + ESG + GATE 1 EVTO 20 + 18 8 RIN CIN 8 RSOURCE 7 LSOURCE 3 SOURCE 6 8 - VTO + 6 21 MOS1 MOS2 16
rev 12/12/94
DPLCAP 10 5 LDRAIN RSCL1 RSCL2 + 51 5 51 ESCL 50 RDRAIN EBREAK 11 17 18 + DBODY DBREAK DRAIN 2
1 1 1 81
9
LGATE RGATE
VBAT 8 19 DC 1 VTO 21 6 0.583 ESCL 51 50 VALUE = {(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)*1e6/176,6))} .MODEL DBDMOD D (IS = 3.61e-13 RS = 5.06e-3 TRS1 = 3.05e-3 TRS2 = 7.57e-6 CJO = 2.16e-9 TT = 2.18e-8) .MODEL DBKMOD D (RS = 1.66e-1 TRS1 = -2.97e-3 TRS2 = 7.57e-6) .MODEL DPLCAPMOD D (CJO = 0.96e-9 IS = 1e-30 N = 10) .MODEL MOSMOD NMOS (VTO = 2.313 KP = 53.82 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL RBKMOD RES (TC1 = 8.95e-4 TC2 = -1e-7) .MODEL RDSMOD RES (TC1 = 3.92e-3 TC2 = 1.29e-5) .MODEL RSCLMOD RES (TC1 = 2.03e-3 TC2 = 0.45e-5) .MODEL RVTOMOD RES (TC1 = -2.27e-3 TC2 = -5.75e-7) .MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.82 VOFF= -2.82) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.82 VOFF= -4.82) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.67 VOFF= 2.33) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2.33 VOFF= -2.67) .ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-circuit for the Power MOSFET Featuring Global Temperature Options; written by William J. Hepp and C. Frank Wheatley.
5-37

▲Up To Search▲

Price & Availability of RFD16N03L

	To Download RFD16N03L Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .